Download:
DS Written Notes
Microprocessor Handwritten Programs
Download --> Print ---> Take ---> Copy it in exam... :D
See Similar Posts:
Showing posts with label Digital-Electronics-Microprocessors. Show all posts
Showing posts with label Digital-Electronics-Microprocessors. Show all posts
Handwritten Notes for Discrete Mathematics and Digital Electronics - WASE Open Exam
Handwritten Notes for Discrete Mathematics and Digital Electronics specially for WASE Open Book exams.
Download:
DS Written Notes
Microprocessor Handwritten Programs
See Similar Posts:
Download:
DS Written Notes
Microprocessor Handwritten Programs
See Similar Posts:
Notes for Discrete Mathematics and Digital Electronics WASE Open Exam
Best of Luck for your exam.
Download Discrete Mathematics and Digital Electronics WASE Open Exam Notes
See Similar Posts:
WASE - Microprocessor Programs
Microprocessor Programs
like :
Addition,
Subtraction,
Display Messaging,
Multiplication,
Division,
Square,
etc...
Click to Download
Click here for 8086 Assembly Language Programming
See Similar Posts:
Digital Electronics MCQ's
Download Digital-Electronics-Microprocessors Objectives Questions.
Download File1
Download File2
Download File3
Digital Electronics MCQ's
Hey guys here is the link for Digital electronics MCQ's
Follow the below link
http://bit.ly/A77IFf
Microprocessor - True or False Questions
TRUE-FALSE
-------------------
1. For a 16MB memory, memory location 50024 will always have a value which is greater than the value in location 5 (False)
2. All 8-bit address spaces are byte addressable (False)
3. An 8-bit register contains a value, The value 1 is written into it, the original value can still be recovered (False)
4. It is possible to have circuits that contains both P type and N type transistors (True)
5. It is possible for a 3:8 decoder to have 3 out of the eight outputs asserted. (False)
6. It is possible to have a 5 input and gate (True)
7. For a two input NAND gate, it is possible that 3 out of 4 transistors are open circuited at a given time (False)
8. The p type and n type transistors of an inverter can never both be short circuited at the same time (True)
9. Addressability of a machine can never be greater than its address space (False)
10. A function (call it *) is associative if (a*b)*c = a*(b*c). Using this definition, NAND is an associative function (False)
11. DeMorgan's Law shows that we can implement any and-or function with a nand-nand function. If the number of transisors through which a signal has to pass determines the delay of that signal, a nand-nand realisation of a function is faster than and-or realisation Hint: examine the transistor implementations of and, or, and nand. (True)
12. For a logic circuit to work as a storage element it is necessary that the ouput be fed back to the input (True).
13. If a memory has addressability of 4 bits then we need 2 bits to specify the address space (False)
15. The two outputs of a latch are always the complement of each other (True)
Microprocessor - Fill in the Blank Questions
Fill in Blanks
--------------
20. If a logical variable A is applied to an inverter, and the output of that inverter is applied to the input of a second inverter, the output of that second inverter is (A).
--------------
(Note: Blank is indicated by parentheses which contains the answer)
1. To implement an n input NOR gate (by generalizing the circuit for a 2-input NOR gate shown in the textbook) we would need (2*n) transistors.
2. A (MUX) is used to select one of many inputs.
3. If A[15:0] = 1000110001110001, A[12:9] = (0110).
4. A 2 bit by 2-bit multiplier circuit will have (4) output bits.
5. It is possible to make a two input OR gate using (3) two input nand gates
6. A memory, consisting of 16K entries, is 13-bit addressable. It contains (13*2^14) bits of storage.
7.If 16 bits are used to specify the address space of a memory, the memory has ( 65536 ) uniquely identifiable locations.
8. A decoder with n inputs can have no more than (2^n) outputs.
9. If the 2 inputs of a 2 input nand gate are connected together, then the function of the nand gate is that of a/an (INVERTER).
10. A (DECODER) is helpful in identifying the opcode of an instruction.
11. At any time there are exactly (TWO) transistors open circuited in a 2 input nand gate.
12. The function NOT { AB+CD } can be implemented using a minimum of ( 8 ) transistors .
13. A circuit for adding two n bit numbers, like the one in the textbook, requires (n) full adders with ( n+1 ) bits of output.
14. A full adder generates a carry in exactly (4) of the (8) possible combinations of its input .
15. If the delay from the inputs { A,B, Cin } to Sum is 1.5 D and to Cout is 1.0 D, then the delay of a four bit adder is ( 4.5D )
16. When the gate is supplied with 0v the p type transistor acts as a (closed circuit).
17. When the gate of a n type transistor is supplied with 0 volts, the n type transistor acts like a (open circuit).
18. One can write into a gated D latch only while the (WE) signal is asserted.
19. We clear an R-S latch by momentarily setting the (R) signal to (0).
Microprocessor - Multiple Choice Questions
Multiple Choice
---------------
---------------
#1. The minimum number of transistors required to implement a two input AND gate is
a. 2
b. 4
c. 6
d. 8
Answer: c
2. Using DeMorgan's Theorem we can convert any AND-OR structure into
a. NAND-NAND
b. OR-NAND
c. NAND-NOR
d. NOR-NAND
Answer: a
3. For a memory with a 16-bit address space, the addressability is
a. 16 bits
b. 8 bits
c. 2^16 bits
d. Cannot be determined
Answer: d
4. Because we wish to allow each ASCII code to occupy one location in memory, most memories are _____ addressable.
a. BYTE
b. NIBBLE
c. WORD (16 bits)
d. DOUBLEWORD (32 bits)
Answer: a
5. Circuit A is a 1-bit adder; circuit B is a 1 bit multiplier.
a. Circuit A has more gates than circuit B
b. Circuit B has more gates than circuit A
c. Circuit A has the same number of gates as circuit B
(Hint: Construct the truth table for the adder and the multiplier)
Answer: a
6. When the write enable input is not asserted, the gated D latch ______ its output.
a. can not change
b. clears
c. sets
d. complements
Answer: a
7. A structure that stores a number of bits taken "together as a unit" is a
a. gate
b. mux
c. decoder
d. register
Answer: d
8. We say that a set of gates is logically complete if we can build any circuit without using any other kind of gates. Which of the following sets are logically complete
a. set of {AND,OR}
b. set of {EXOR, NOT}
c. set of {AND,OR,NOT}
d. None of the above
Answer: c
9. Of the following circuits, the one which involves storage is
a. RS Latch
b. mux
c. nand
d. decoder
Answer: a
10. If the number of address bits in a memory is reduced by 2 and the
addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory)
a. doubles
b. remains unchanged
c. halves
d. increases by 2^(address bits)/addressability
Answer : c
12. If m is a power of 2, the number of select lines required for an m-input mux is:
a. m
b. 2^m
c. log2 (m)
d. 2*m
Answer: c
13. For the number A[15:0] = 0110110010001111, A[14:13 ] is ______ A[3:2].
a. less than
b. greater than
c. the same as
d . cannot be determined
Answer: c
14. Which of the following conditions is not allowed in an RS latch?
a. R is asserted, S is asserted
b. R is asserted, S is negated
c. R is negated, S is asserted
d. R is negated, S is negated
Answer: a
15. Which of the following pair of gates can form a latch?
a. a pair of cross coupled OR
b. a pair of cross copled AND
c. a pair of cross coupled NAND
d. a cross coupled NAND/OR
Answer: c
Microprocessor 8085 Programs
1) Add Positive Nos.
LXI H, 2100
MVI B, 0
MVI D, FF
MVI C, 5
START: MOV A, M
RLC JC
NEXT
RRC
ADD B
CMP D
JC END
MOV B,
A
NEXT: INX H
DCR C
JNZ
START
END: STA 2000
HLT
2) Bubble Sort
MVI B, 05
START: LXI H,
2100
MVI C, 04
BACK: MOV A,
M
INX H
CMP M
JC END
STA 2200
MOV A, M
DCX H
MOV M, A
LDA 2200
INX H
MOV M, A
END: DCR
C
JNZ BACK
DCR B
JNZ START
HLT 
3) Exchanging the
Array Elements (Swap 2 Arrays)
LXI H, 2100
LXI D, 2200
MVI C, 0A
START: MOV A, M
STA 2300
LDAX D
MOV M, A
LDA 2300
STAX D
INX H
INX D
DCR C
JNZ START
HLT
4) Find the Highest
No in an Array
LXI H, 2100
MVI C, 03
MOV A, M
DCR C
INX H
START: CMP M
JNC NEXT
MOV A, M
NEXT: INX H
DCR C
JNZ START
STA 2200
HLT
Important Topics for MicroProcessor
Important Topics for MicroProcessor :
1. DESIGN OF MUX,COUNTERS K
MAPS ,DE CODERS BOOLEAN
EXPRESSION REDUCTION USING
THHOREMS
2. MAKE A LIST OF 1 BYTE, 2BYTE
AND 3 BYTE INSTRUCTIONS
3. WRITE A PROGRAM TO ADD TWO 8
BIT NUMBERS STORE THE SUM
AND CARRY CALCULATE THE
NUMBER OF MEMORY LOCATIONS TO
STORE PROGRA,DATA AND OUTPUT
4. T STATE CALCULATION FOR
LOOP AND NESTED LOOPS
5. PREPARE CONTROL WORD FOR
THE FALLOWING
- A. 8253
- B. 8255
- C. INTERUPT CONTROL WORD
6. GO THROUGH DIAGRAMS IN
- A. I\O INTERFACING
- B. MEMORY INTERFACING
7. GO THROUGH M CYCLE
DIAGRAM
8. IN CHAPTER NO 17 DIAGRAM
OF KEY BOARD INTERFACE
9. BCD TO 7 SEGMENT DISPLAY
IN DETAIL
10. SQUARE
WAVE GENERATION BY USING 8253 CHIP
8085 OPCODES
8085 OPCODES:
DATA TRANSFER:
40,
MOV B B, 4 50, MOV D B, 4 60, MOV H B, 4 70, MOV M B, 7 06,MVI B 8,7
41,
MOV B C, 4 51, MOV D C, 4 61, MOV H C, 4 71, MOV M C, 7 0E,MVI C 8,7
42,
MOV B D, 4 52, MOV D D, 4 62, MOV H D, 4 72, MOV M D, 7 16,MVI D 8,7
43, MOV B E, 4 53, MOV D E, 4 63, MOV H E, 4 73, MOV M E, 7 1E,MVI E 8,7
44, MOV B H, 4 54, MOV D H, 4 64, MOV H H, 4 74, MOV M H, 7 26,MVI H 8,7
45,
MOV B L, 4 55, MOV D L, 4 65, MOV H L, 4 75, MOV M L, 7 2E,MVI L 8,7
46,
MOV B M, 7 56, MOV D M, 7 66, MOV H M, 7 77, MOV M A, 7 36,MVI M 8,10
47,
MOV B A, 4 57, MOV D A, 4 67,
MOV H A, 4 78, MOV A B, 4 3E,MVI A 8,7
48,
MOV C B, 4 58, MOV E B, 4 68,
MOV L B, 4 79, MOV A C, 4
49,
MOV C C, 4 59, MOV E C, 4 69,
MOV L C, 4 7A, MOV A D, 4
4A,
MOV C D, 4 5A, MOV E D, 4 6A, MOV L D, 4 7B, MOV A E, 4
4B, MOV C E, 4 5B, MOV E E, 4 6B, MOV L E, 4 7C, MOV A H, 4
4C, MOV C H, 4 5C, MOV E H, 4 6C, MOV L H, 4 7D, MOV A L, 4
4D, MOV C L, 4 5D, MOV E L, 4 6D, MOV L L, 4 7E, MOV A M, 7
4E, MOV C M, 7 5E, MOV E M, 7 6E, MOV L M, 7 7F, MOV A A, 4
4F,
MOV C A, 4 5F, MOV E A, 4 6F, MOV L A, 4
LOAD:
0A,LDAX
B,7 01,LXI B 16,10 D3,OUT 8,10 E1,POP H,10
1A,LDAX
D,7 11,LXI D 16,10 DB,IN 8,10 F1,POP PSW,10
2A,LHLD
16,16 21,LXI H 16,10 C5,PUSH B,12
3A,LDA
16,13 31,LXI SP 16,10 D5,PUSH D,12
02,STAX
B,7 F9,SPHL,6 E5,PUSH H,12
12,STAX
D,7 E3,XTHL,16 F5,PUSH PSW,12
22,SHLD
16,16 EB,XCHG,4 C1,POP B,10
32,STA
16,13 EB,XCHG,4 D1,POP D,10
ARITHMATIC:
80,ADD B,4 85,ADD L,4 8A,ADC D,4 8F,ADC A,4 90,SUB B,4 96,SUB M,7
81,ADD C,4 86,ADD M,7 8B,ADC E,4 C6,ADI 8,7 91,SUB C,4 97,SUB A,4
82,ADD D,4 87,ADD A,4 8C,ADC
H,4 CE,ACI 8,7 92,SUB D,4 98,SBB B,4
83,ADD E,4 88,ADC B,4 8D,ADC
L,4 93,SUB
E,4 99,SBB C,4
84,ADD H,4 89,ADC C,4 8E,ADC M,7 94,SUB H,4 9A,SBB D,4
95,SUB L,4 9B,SBB E,4
9C,SBB H,4 09,DAD B,10 0C,INR C,4 3C,INR A,4 0D,DCR C,4 3D,DCR A,4
9D,SBB L,4 19,DAD D,10 14,INR D,4 03,INX B,6 15,DCR D,4 0B,DCX
B,6
9E,SBB M,7 29,DAD H,10 1C,INR E,4 13,INX D,6 1D,DCR E,4 1B,DCX
D,6
9F,SBB A,4 39,DAD SP,10 24,INR
H,4 23,INX H,6 25,DCR H,4 2B,DCX
H,6
D6,SUI
8,7 27,DAA,4 2C,INR
L,4 33,INX SP,6 2D,DCR L,4 3B,DCX SP,6
DE,SBI
8,7 04,INR B,4 34,INR
M,7 05,DCR B,4 35,DCR M,7
LOGICAL:
A0,ANA B,4 B0,ORA B,4 FE,CPI
8,4 CF,RST1,12 C8,RZ,6
A1,ANA C,4 B1,ORA C,4 07,RLC,4 D7,RST2,12 D0,RNC,6
A2,ANA D,4 B2,ORA D,4 0F,RRC,4 DF,RST3,12 D8,RC,6
A3,ANA E,4 B3,ORA E,4 17,RAL,4 E7,RST4,12 E0,RPO,6
A4,ANA H,4 B4,ORA H,4 1F,RAR,4 EF,RST5,12 E8,RPE,6
A5,ANA L,4 B5,ORA L,4 2F,CMA,4 F7,RST6,12 F0,RP,6
A6,ANA M,7 B5,ORA L,4 3F,CMC,4 FF,RST7,12 F8,RM,6
A7,ANA A,4 B6,ORA M,7 C3,JMP
AD,10 CD,CALL AD,18 00,NOP,4
E6,ANI 8,7 B7,ORA
A,4 C2,JNZ AD,7 C4,CNZ
AD,9 76,HLT,5
A8,XRA B,4 F6,ORI 8,7 CA,JZ
AD,7 CC,CZ AD,9 F3,DI,4
A9,XRA C,4 B8,CMP B,4 D2,JNC
AD,7 D4,CNC AD,9 FB,EI,4
AA,XRA D,4 B9,CMP C,4 DA,JC
AD,7 DC,CC AD,9 20,RIM,4
AB,XRA E,4 BA,CMP D,4 E2,JPO
AD,7 E4,CPO AD,9 30,SIM,4
AC,XRA H,4 BB,CMP E,4 EA,JPE
AD,7 EC,CPE AD,9
AD,XRA L,4 BC,CMP H,4 F2,JP AD,7 F4,CP
AD,9
AE,XRA M,7 BD,CMP L,4 FA,JM AD,7 FC,CM
AD,9
AF,XRA A,4 BE,CMP M,7 E9,PCHL,6 C9,RET,10
EE,XRI 8,7 BF,CMP A,4 C7,RST0,12 C0,RNZ,6
Microprocessor Programs
Microprocessor
Programs :
Multiplication of Two 4 bit Numbers
XRA
A
LXI
H, 2100
MOV
B,M
INX
H
L1: ADD M
DCR
B
JNZ L1
STA
2102
HLT
Multiplication of Two 8-bit Numbers
XRA A
MOV B,A
LXI H, 1100
MOV C,M
INX H
L2: ADD M
JNC L1
INR B
L1: DCR C
JNZ L2
INX H
MOV M,A
INX H
MOV A,B
MOV M,A
HLT
Addition Of Two Numbers:
LDA 4150
MOV B,A
LDA 4151
ADD M
STA 4152
HLT
Addition Of Two no(method 2)
LXI H,2050
MOV A,M
INX H
ADD M
INX H
MOV A,B
HLT
Subtraction of
Two no
LDA 4150
MOV B,A
LDA 4151
SUB B
STA 4152
HLT
Method 2 : Subtraction of Two No
LXI H,2050
MOV A,M
INX H
SUB M
INX H
MOV M,A
HLT
Biggest of Numbers
LXI H,4150
MOV C,M
INX H
MOV A,M
LOP: INX H
CMP M
JNC LOP1
MOV A,M
LOP1 DCR C
JNZ LOP
MOV M,A
HLT
Smallest of the No:
LXI H,4150
MOV C,M
MOV A,M
INX H
CMP M
JC LOOP1
MOV A,M
LOOP1:DCR C
JNZ LOOP
MOV M,A
HLT
Division
XRA
A
MOV
C,A
LXI
H,4150
MOV
B,M
INX
H
MOV
A,M
P1: SUB B
JC
L1
INC
C
JMP
P1
L1: ADD B
STA
4153
MOV
AMC
STA
4152
HLT
Block Transfer
LXI
H,2100
LXI
D,2200
MVI
C,0A
L1: MVI A,M
STAX
D
INX
H
INX
D
DCR
C
JNZ
L1
HLT
RST
7
Ascending Order
LXI H,4150
MOV C,M
L1: MOV B,C
INX H
MOV A,M
PUSH H
DCR B
JZ LA1
L2: INX H
CMP M
JC L3
MOV D,A
MOV A,M
MOV M,D
L3: DCR B
JNZ L2
POP H
MOV M,A
DCR C
JMP L1
LA1: HLT
Decending Order:
LXI
H,4150
MOV
C,M
L1: MOV B,C
INX
H
MOV
A,M
PUSH
H
DCR
B
JZ
LA1
L2: INX H
CMP
M
JNC
L3
MOV
D,A
MOV
A,M
MOV
M,D
L3: DCR B
JNZ
L2
POP
H
MOV
M,A
DCR
C
JMP
L1
HLT
Binary To BCD
LXI H,2101
MVI C,04
AGAIN: ORA M
DCR C
JZ FINISH
RLC
FINISH: INX H
JMP AGAIN
INX H
CPI OA
JC RESULT
MVI A,EE
RESULT: MOV M,A
MOV M,C
HLT
BCD To Binary
MVI D,08
LXI H,2100
MVI C,04
MOV B,M
AGAIN: MOV A,B
INX H
ANA D
JZ LOOP
MVI A,01
MOV A,D
RRC
MOV D,A
DCR C
JNZ AGAIN
HLT
Decimal to Hexa
XRA A
MOV C,A
LXI H,2100
MOV B,M
L1: ADI 64
JNC L2
INR C
DCR B
L2: JNZ L1
MOV D,A
INX H
MOV B,M
XRA A
ADI 0A
L3: DCR B
JNZ L3
INX H
ADD M
ADD D
JNC L4
INR C
L4: INX H
MOV M,C
INX H
MOV M,A
HLT
Hexa Decimal to Decimal
LXI
H,4150
LXI
B,0000
MOV
A,M
SUI
64
JC L2
INR
B
JMP
L1
ADI
64
SUI
OA
JC
L4
INR
C
MOV
M,B
MOV
B,A
MOV
A,C
RLC
RLC
RLC
RLC
ADD
B
INX
H
MOV
M,A
HLT
Subscribe to:
Posts (Atom)
WASE open book exams - June 2013
Hey waseians, All the best for exams... ☺ Exams time table Useful posts for open book exam Semester 3 materials Get ready...
-
Hey waseians, All the best for exams... ☺ Exams time table Useful posts for open book exam Semester 3 materials Get ready... -
CDC :- Chennai Development Center BDC :- Bangalore Development Center GNDC :- Greater Noida Development Center HDC :- Hyderabad Dev...