Discrete Mathematical Structures - Sets and Subsets


Sets and Subsets :

Sets and Subsets
Download Notes for :  
Download1
Download2

The Notes include :

Definitions:
Set: A set is a collection of well-defined objects (elements/members). The elements of the set are said to belong to (or be contained in) the set.
A set may be itself be an element of some other set.
A set can be a set of sets of sets and so on.
Sets will be denoted be capital letters A, B, C, ...
Elements will be denoted by lower case letters a, b, c, ....  x, y, z.


There are five ways to describe a set.
1. Describe a set by describing the properties of the members of the set.
2. Describe a set by listing its elements.
3. Describe a set by its characteristic functions
4. Describe a set by a recursive formula.
5. Describe a set by an operation (such as union, intersection, complement etc.,) on some other
    sets.

Venn diagrams: Venn diagrams are used to visualise various properties of the set operations.
The Universal Set is represented by a large rectangular area.


Distributive and DeMorgan’s Laws can be established from Venn diagrams.

Distributive laws
AÈ(BÇC) = (AÈB) Ç (AÈC) 

Exercises:
 1.         Let A = {1, 2, 3, 4, 5}. Which of the following sets are equal to A?
a.             {4, 1, 2, 3, 5}
b.            {2, 3, 4}
c.             {1, 2, 3, 4, 5, 6}
d.            {x | x is an integer and x2 £ 25}
e.             {x | x is a positive integer and x £ 5}
f.             {x | x is a positive rational number and x £ 5}
etc...

Sequences
A sequence is a list of objects arranged in a definite order; a first element, second element, third element, and so on. It is classified as finite sequence and infinite sequence. The elements may all be different, or some may be repeated.
Examples:
1.      The sequence 1, 0, 0, 1, 0, 1, 0, 0, 1, 1 is a finite sequence with repeated items.
2.      The sequence 1, 3, 5, 7, 9, 11, 13, 15 is a finite sequence with different items.
3.      The sequence 3, 8, 13, 18, … is an infinite sequence.

etc...

Characteristic Functions
If A is a subset of a universal set U, the characteristic function fA of A is defined for each x Î U as:
            fA(x)    = 1, if x Î A
                        = 0, if x Ï A.


etc...

Strings

Given a set A, we can construct the set A* consisting of all finite sequences of elements of A. Often, the set A is not a set of numbers, but some set of symbols and Set A is called an alphabet, and the finite sequences in A* are called words or strings from A. The empty sequence or empty string contains no symbols and denoted as Ù.
Example:


etc...
 
Regular Expressions
A regular expression (over A) is a string constructed from the elements of A and the symbols (, ), Ú, *, Ù, according to the following definition.
RE1. The symbol Ù is a regular expression.
RE2. If x Î A, the symbol x is a regular expression.
RE3. If a and b are regular expressions, then the expression ab is regular.
RE4. If a and b are regular expressions, then the expression (aÚb) is regular.
RE5. If a is a regular expression, then the expression (a)* is regular.

Examples:
1.      0*(0Ú1)*

etc...
Matrices

A matrix is a rectangular array of numbers arranged in m horizontal rows and n vertical columns.
            a11          a12          …             a1n
            a21          a22          …             a2n
A =      .           .           .           .
            .           .           .           .
am1         am2         …             amn

A = [ aij ].

etc...



Boolean matrix
A Boolean matrix is an m x n matrix whose entries are either zero or one.

Boolean matrix operations
Let A and B be m x n Boolean matrices.

etc...

WASE - MS Schedule for 1st Semester 2011-2012

        MS Semester-1
 
Month
Date
Description
Jan
2012
21
Session
1
28
Session
2
Feb
2012
4
Session
3
11
Session
4
18
Session 5
25
Session
6
March 2012
3
Session
7
10
Holi
17
Session 8
25 (Sunday)
Mid sem
Apr 2012
1
(Sunday)
Mid sem
7
Session
9
14
Session 10
21
Session 11
28
Session 12
May 2012
5
Session
13
12
Session
14
19
Session 15
26
Session 16
Jun
2012
3
(Sunday)
Compre
10
(Sunday)
Compre

Microprocessor - True or False Questions


true or false

TRUE-FALSE 
-------------------

1. For a 16MB memory, memory location 50024 will always have a value which is greater than the value in location 5 (False)

2. All 8-bit address spaces are byte addressable (False)

3. An 8-bit register contains a value, The value 1 is written into it, the original value can still be recovered (False)

4. It is possible to have circuits that contains both P type and N type transistors  (True)

5. It is possible for a 3:8 decoder to have 3 out of the eight outputs asserted. (False)

6. It is possible to have a 5 input and gate (True)

7. For a two input NAND gate, it is possible that 3 out of 4 transistors are open circuited at a given time (False)

8. The p type and n type transistors of an inverter can never both be short circuited at the same time (True)

9.  Addressability of a machine can never be greater than its address space (False)

10. A function (call it *) is associative if (a*b)*c = a*(b*c).  Using this definition, NAND is an associative function (False)

11. DeMorgan's Law shows that we can implement any and-or function with a nand-nand function.  If the number of transisors through which a signal has to pass determines the delay of that signal, a nand-nand realisation of a function is faster than and-or realisation Hint: examine the transistor implementations of and, or, and nand. (True)

12. For a logic circuit to work as a storage element it is necessary that the ouput be fed back to the input (True).

13. If a memory has addressability of 4 bits then we need 2 bits to specify the address space (False)

14. It is not possible to have a 1 bit register (False)


15. The two outputs of a latch are always the complement of each other (True)
 

Microprocessor - Fill in the Blank Questions

Fill in Blanks
-------------- 
questions


(Note: Blank is indicated by parentheses which contains the answer)

1. To implement an n input NOR gate (by generalizing the circuit for a 2-input NOR gate shown in the textbook) we would need (2*n) transistors.

2. A (MUX) is used to select one of many inputs.

3. If A[15:0] = 1000110001110001, A[12:9] = (0110).

4. A 2 bit by 2-bit multiplier circuit will have (4) output bits.

5. It is possible to make a two input OR gate using (3) two input nand gates

6. A memory, consisting of 16K entries, is 13-bit addressable. It contains (13*2^14) bits of storage.

7.If 16 bits are used to specify the address space of a memory, the memory has ( 65536 ) uniquely identifiable locations.

8. A decoder with n inputs can have no more than (2^n) outputs.

9. If the 2 inputs of a 2 input nand gate are connected together, then the function of the nand gate is that of a/an (INVERTER).

10. A (DECODER) is helpful in identifying the opcode of an instruction.

11. At any time there are exactly (TWO) transistors open circuited in a 2 input nand gate.

12. The function NOT { AB+CD } can be implemented using a minimum of ( 8 ) transistors .

13. A circuit for adding two n bit numbers, like the one in the textbook, requires (n) full adders with ( n+1 )  bits of output.

14. A full adder generates a carry in exactly (4)  of the (8)  possible combinations of its input .

15. If the delay from the inputs { A,B, Cin } to Sum is 1.5 D and to Cout is 1.0 D, then the delay of a four bit adder is  ( 4.5D )

16. When the gate is supplied with 0v the p type transistor acts as a (closed circuit).

17. When the gate of a n type transistor is supplied with 0 volts, the n type transistor acts like a (open circuit).

18. One can write into a gated D latch only while the (WE) signal is asserted.

19. We clear an R-S latch by momentarily setting the (R) signal to (0).

20. If a logical variable A is applied to an inverter, and the output of that inverter is applied to the input of a second inverter, the output of that second inverter is (A).

Microprocessor - Multiple Choice Questions

Multiple Choice
---------------


#1. The minimum number of transistors required to implement a two input AND gate is

a. 2
b. 4
c. 6
d. 8
Answer: c

2. Using DeMorgan's Theorem we can convert any AND-OR structure into

a. NAND-NAND
b. OR-NAND
c. NAND-NOR
d. NOR-NAND
Answer: a


3. For a memory with a 16-bit address space, the addressability is
a. 16 bits
b. 8 bits
c. 2^16 bits
d. Cannot be determined
Answer: d


4. Because we wish to allow each ASCII code to occupy one location in memory, most memories are _____ addressable.
a. BYTE
b. NIBBLE
c. WORD (16 bits)
d. DOUBLEWORD (32 bits)
Answer: a


5. Circuit A is a 1-bit adder; circuit B is a 1 bit multiplier.

a. Circuit A has more gates than circuit B
b. Circuit B has more gates than circuit A
c. Circuit A has the same number of gates as circuit B

(Hint: Construct the truth table for the adder and the multiplier)

Answer: a


6. When the write enable input is not asserted, the gated D latch ______ its output.
a. can not change
b. clears
c. sets
d. complements
Answer: a

7.  A structure that stores a number of bits taken "together as a unit" is a
a. gate
b. mux
c. decoder
d. register
Answer: d


8. We say that a set of gates is logically complete if we can build any circuit without using any other kind of gates.  Which of the following sets are logically complete
a. set of {AND,OR}
b. set of {EXOR, NOT}
c. set of {AND,OR,NOT}
d. None of the above
Answer: c


9. Of the following circuits, the one which involves storage is
a. RS Latch
b. mux
c. nand
d. decoder
Answer: a


10.  If the number of address bits in a memory is reduced by 2 and the
addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory)
a. doubles
b. remains unchanged
c. halves
d. increases by 2^(address bits)/addressability
Answer : c


12.  If m is a power of 2, the number of select lines required for an m-input mux is:

a. m
b. 2^m
c. log2 (m)
d. 2*m
Answer: c

13.  For the number A[15:0] = 0110110010001111,  A[14:13] is ______  A[3:2].

a. less than
b. greater than
c. the same as
d . cannot be determined
Answer: c


14. Which of the following conditions is not allowed in an RS latch?

a. R is asserted, S is asserted
b. R is asserted, S is negated
c. R is negated, S is asserted
d. R is negated, S is negated
Answer: a


15. Which of the following pair of gates can form a latch?
a. a pair of cross coupled OR
b. a pair of cross copled AND
c. a pair of cross coupled NAND
d. a cross coupled NAND/OR
Answer: c

Microprocessor 8085 Programs

1) Add Positive Nos.

 
  LXI H, 2100
  MVI B, 0
  MVI D, FF
  MVI C, 5
START: MOV A, M
               RLC JC
               NEXT
               RRC
               ADD B
               CMP D
               JC END
               MOV B, A
  NEXT:  INX H
                DCR C
                JNZ START
      END: STA 2000
                HLT

2) Bubble Sort

MVI B, 05
START:           LXI H, 2100
MVI C, 04
BACK:            MOV A, M
INX H
CMP M
JC END
STA 2200
MOV A, M
DCX H
MOV M, A
LDA 2200
INX H
MOV M, A
END:               DCR C
JNZ BACK
DCR B
JNZ START
HLT dot

3) Exchanging the Array Elements (Swap 2 Arrays)

 LXI H, 2100
 LXI D, 2200
 MVI C, 0A
START:            MOV A, M
 STA 2300
 LDAX D
 MOV M, A
 LDA 2300
 STAX D
 INX H
 INX D
 DCR C
 JNZ START
 HLT
dot          

4) Find the Highest No in an Array

LXI H, 2100
MVI C, 03
MOV A, M
DCR C
INX H
START:           CMP M
 JNC NEXT
 MOV A, M
 NEXT:            INX H
 DCR C
 JNZ START
 STA 2200
 HLT

Decimal - Hexadecimal - Binary conversion table

Decimal - hexadecimal - binary conversion table :

Decimal-hexadecimal-binary-conversion


Dec Hex Bin
Dec Hex Bin
0 0 0
128 80 10000000
1 1 1
129 81 10000001
2 2 10
130 82 10000010
3 3 11
131 83 10000011
4 4 100
132 84 10000100
5 5 101
133 85 10000101
6 6 110
134 86 10000110
7 7 111
135 87 10000111
8 8 1000
136 88 10001000
9 9 1001
137 89 10001001
10 a 1010
138 8a 10001010
11 b 1011
139 8b 10001011
12 c 1100
140 8c 10001100
13 d 1101
141 8d 10001101
14 e 1110
142 8e 10001110
15 f 1111
143 8f 10001111
16 10 10000
144 90 10010000
17 11 10001
145 91 10010001
18 12 10010
146 92 10010010
19 13 10011
147 93 10010011
20 14 10100
148 94 10010100
21 15 10101
149 95 10010101
22 16 10110
150 96 10010110
23 17 10111
151 97 10010111
24 18 11000
152 98 10011000
25 19 11001
153 99 10011001
26 1a 11010
154 9a 10011010
27 1b 11011
155 9b 10011011
28 1c 11100
156 9c 10011100
29 1d 11101
157 9d 10011101
30 1e 11110
158 9e 10011110
31 1f 11111
159 9f 10011111
32 20 100000
160 a0 10100000
33 21 100001
161 a1 10100001
34 22 100010
162 a2 10100010
35 23 100011
163 a3 10100011
36 24 100100
164 a4 10100100
37 25 100101
165 a5 10100101
38 26 100110
166 a6 10100110
39 27 100111
167 a7 10100111
40 28 101000
168 a8 10101000
41 29 101001
169 a9 10101001
42 2a 101010
170 aa 10101010
43 2b 101011
171 ab 10101011
44 2c 101100
172 ac 10101100
45 2d 101101
173 ad 10101101
46 2e 101110
174 ae 10101110
47 2f 101111
175 af 10101111
48 30 110000
176 b0 10110000
49 31 110001
177 b1 10110001
50 32 110010
178 b2 10110010
51 33 110011
179 b3 10110011
52 34 110100
180 b4 10110100
53 35 110101
181 b5 10110101
54 36 110110
182 b6 10110110
55 37 110111
183 b7 10110111
56 38 111000
184 b8 10111000
57 39 111001
185 b9 10111001
58 3a 111010
186 ba 10111010
59 3b 111011
187 bb 10111011
60 3c 111100
188 bc 10111100
61 3d 111101
189 bd 10111101
62 3e 111110
190 be 10111110
63 3f 111111
191 bf 10111111
64 40 1000000
192 c0 11000000
65 41 1000001
193 c1 11000001
66 42 1000010
194 c2 11000010
67 43 1000011
195 c3 11000011
68 44 1000100
196 c4 11000100
69 45 1000101
197 c5 11000101
70 46 1000110
198 c6 11000110
71 47 1000111
199 c7 11000111
72 48 1001000
200 c8 11001000
73 49 1001001
201 c9 11001001
74 4a 1001010
202 ca 11001010
75 4b 1001011
203 cb 11001011
76 4c 1001100
204 cc 11001100
77 4d 1001101
205 cd 11001101
78 4e 1001110
206 ce 11001110
79 4f 1001111
207 cf 11001111
80 50 1010000
208 d0 11010000
81 51 1010001
209 d1 11010001
82 52 1010010
210 d2 11010010
83 53 1010011
211 d3 11010011
84 54 1010100
212 d4 11010100
85 55 1010101
213 d5 11010101
86 56 1010110
214 d6 11010110
87 57 1010111
215 d7 11010111
88 58 1011000
216 d8 11011000
89 59 1011001
217 d9 11011001
90 5a 1011010
218 da 11011010
91 5b 1011011
219 db 11011011
92 5c 1011100
220 dc 11011100
93 5d 1011101
221 dd 11011101
94 5e 1011110
222 de 11011110
95 5f 1011111
223 df 11011111
96 60 1100000
224 e0 11100000
97 61 1100001
225 e1 11100001
98 62 1100010
226 e2 11100010
99 63 1100011
227 e3 11100011
100 64 1100100
228 e4 11100100
101 65 1100101
229 e5 11100101
102 66 1100110
230 e6 11100110
103 67 1100111
231 e7 11100111
104 68 1101000
232 e8 11101000
105 69 1101001
233 e9 11101001
106 6a 1101010
234 ea 11101010
107 6b 1101011
235 eb 11101011
108 6c 1101100
236 ec 11101100
109 6d 1101101
237 ed 11101101
110 6e 1101110
238 ee 11101110
111 6f 1101111
239 ef 11101111
112 70 1110000
240 f0 11110000
113 71 1110001
241 f1 11110001
114 72 1110010
242 f2 11110010
115 73 1110011
243 f3 11110011
116 74 1110100
244 f4 11110100
117 75 1110101
245 f5 11110101
118 76 1110110
246 f6 11110110
119 77 1110111
247 f7 11110111
120 78 1111000
248 f8 11111000
121 79 1111001
249 f9 11111001
122 7a 1111010
250 fa 11111010
123 7b 1111011
251 fb 11111011
124 7c 1111100
252 fc 11111100
125 7d 1111101
253 fd 11111101
126 7e 1111110
254 fe 11111110
127 7f 1111111
255 ff 11111111

WASE open book exams - June 2013

Hey waseians, All the best for exams... ☺ Exams time table Useful posts for open book exam Semester 3 materials Get ready...